The board consists of two DSP processors which will process the incoming analog signals. Control logic is implemented in FPGA. The incoming analog signals are received by the dual analog to digital converters. These digital converted analog signals can be communicated to DSPs and also to the host system. Interfacing with the host system is through a PCI bridge. FPGA can also be used for transmitting data either through serial communication or by parallel way. The selection of the mode of communication is by a hardware jumper. PCI-9054 is used for interfacing local bus to host bus.
Processor : Two Tiger SHARC DSP Processors at 250MHz TS101.
FPGA : Xilinx Virtex-II FPGA configured to 32 bit digital I/O.
A/D Converter :Two Single Channel 14-bit ADC Operating at 125MHz.
D/A Converter: Dual Channel 14-bit DAC Operating at 125MHz.
Memory : 6Mbits of in built SRAM per each DSP Processor 32MB SDRAM. 4MB Boot Flash used to boot DSPs and store FPGA Configuration.
PCI : PCI Interface Device PCI-9054, 32-bit PCI 2.2 compliance.
Processor Local bus: 32-bit data and 32-bit address.
Serial Port : Four RS-422 channels and Four TTL outputs.
Connectors : PCI edge connectors E1 (62-pins), E2 (62-pins).
Header : An 1149.1 IEEE complaint JTAG test access port for on Chip Emulation for DSP Processors and FPGA.
Software : Board Support Package (BSP).